Infineon/CYPRESS CY8C4248LQI-BL583

PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4200_BL product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard communication and timing peripherals. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design.

• 32-bit MCU Subsystem
  • 48-MHz Arm Cortex-M0 CPU with single-cycle multiply and DMA
  • Up to 256 KB of flash with Read Accelerator
  • Up to 32 KB of SRAM
• BLE Radio and Subsystem
  • BLE 4.2 support
  • 2.4-GHz RF transceiver with 50-Ω antenna drive
  • Digital PHY
  • Link-Layer engine supporting master and slave modes
  • RF output power: –18 dBm to +3 dBm
  • RX sensitivity: –89 dBm
  • RX current: 18.7 mA
  • TX current: 15.6 mA at 0 dBm
  • RSSI: 1-dB resolution
• Programmable Analog
  • Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes, and ADC input buffering capability. Can operate in Deep Sleep mode.
  • 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging
  • Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
  • Two low-power comparators that operate in Deep Sleep mode
• Programmable Digital
  • Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and data path
  • Cypress-provided peripheral component library, user-defined state machines, and Verilog input
• Power Management
  • Active mode: 1.7 mA at 3-MHz flash program execution
  • Deep Sleep mode: 1.5 μA with watch crystal oscillator (WCO) on
  • Hibernate mode: 150 nA with RAM retention
  • Stop mode: 60 nA
• Capacitive Sensing
  • Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (>5;1) and liquid tolerance
  • Cypress-supplied software component makes capacitive sensing design easy
  • Automatic hardware tuning algorithm (SmartSense™)
• Segment LCD Drive
  • LCD drive supported on all pins (common or segment)
  • Operates in Deep Sleep mode with four bits per pin memory
• Serial Communication
  • Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I²C, SPI, or UART functionality
• Timing and Pulse-Width Modulation
  • Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks
  • Center-aligned, Edge, and Pseudo-random modes
  • Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
• Up to 36 Programmable GPIOs
  • Any GPIO pin can be CapSense, LCD, analog, or digital
  • Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable
• PSoC Creator™ Design Environment
  • Integrated Design Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)
  • API components for all fixed-function and programmable peripherals
• Industry-Standard Tool Compatibility
  • After schematic entry, development can be done with Arm-based industry-standard development tools

• Low-power and portable devices
• Wearable technology
• IoT devices
• Smart home devices
• Health monitoring devices
• Industrial automation
• Sensor networks
• Remote controls
• Data loggers
• Electronic tags
• Wireless communication devices
• Battery-powered devices
• Automotive electronics
• Medical devices
• Security systems
• Asset tracking
• Sports and fitness devices
• Smart agriculture
• Environmental monitoring
• Consumer electronics