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Infineon/CYPRESS S25FL256SAGMFI000

Manufacturer
Infineon/CYPRESS
MPN
S25FL256SAGMFI000
LCSC Part #
C466856
Packaging
SOIC-16-300mil
Customer #
Key Attributes
2.7V~3.6V 256Mbit 133MHz SPI SOIC-16-300mil Memory (ICs)
Datasheetpdf iconInfineon/CYPRESS S25FL256SAGMFI000
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QtyUnit Price(Reference Only)Total Amount
1+$ 5.0744$ 5.07
10+$ 4.9664$ 49.66
30+$ 4.8954$ 146.86
100+$ 4.8243$ 482.43
Standard Packaging240/Full Tube
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerInfineon/CYPRESS
PackagingSOIC-16-300mil
Voltage - Supply2.7V~3.6V
Memory Size256Mbit
Operating temperature-40℃~+85℃
Program / Erase Cycles100,000 cycles
Clock Frequency133MHz
FeaturesWrite enable latch;Power-on reset;Hardware write protection;Software write protection;ECC error correction
Data Retention - TDR (Year)20 Years
Page Programming Time (Tpp)340us
Standby Supply Current70uA
InterfaceSPI
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging240
Sales UnitPiece

Introduction

AI Translation

The Cypress S25FL128S and S25FL256S devices are flash non-volatile memory products using:

  • MirrorBit technology - that stores two data bits in each memory array transistor
  • Eclipse architecture - that dramatically improves program and erase performance
  • 65 nm process lithography This family of devices connect to a host system via a SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO.

Features

AI Translation
  • CMOS 3.0 Volt Core with Versatile I/O
  • SPI with Multi-I/O
  • SPI Clock polarity and phase modes 0 and 3
  • DDR option
  • Extended Addressing: 24- or 32-bit address options
  • Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
  • Multi I/O Command set and footprint compatible with S25FL-P SPI family
  • READ Commands: Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
  • AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address
  • Common Flash Interface (CFI) data for configuration information
  • Programming (1.5 MBps)
  • 256 or 512 Byte Page Programming buffer options
  • Quad-Input Page Programming (QPP) for slow clock systems
  • Automatic ECC-internal hardware Error Correction Code generation with single bit error correction
  • Erase (0.5 to 0.65 MBps)
  • Hybrid sector size option - physical set of thirty two 4-KB sectors at top or bottom of address space with all remaining sectors of 64 KB, for compatibility with prior generation S25-FL devices
  • Uniform sector option - always erase 256-KB blocks for software compatibility with higher density and future devices
  • Cycling Endurance: 100,000 Program-Erase Cycles, minimum
  • Security features
  • OTP array of 1024 bytes
  • Block Protection: Status Register bits to control protection against program or erase of a contiguous range of sectors. Hardware and software control options
  • Advanced Sector Protection (ASP): Individual sector protection controlled by boot code or password
  • Cypress 65 nm MirrorBit Technology with Eclipse Architecture
  • Temperature Range / Grade:
  • Industrial (-40℃ to +85℃)
  • Industrial Plus -40℃ to +105℃
  • Automotive AEC-Q100 Grade 3 (-40℃ to +85℃)
  • Automotive AEC-Q100 Grade 2 (-40℃ to +105℃)
  • Automotive AEC-Q100 Grade 1 (-40℃ to +125℃)