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MICROCHIP PIC24FJ128GB106-I/PT product image
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MICROCHIP PIC24FJ128GB106-I/PTRoHS

Manufacturer
MICROCHIP
MPN
PIC24FJ128GB106-I/PT
LCSC Part #
C220655
Packaging
TQFP-64(10x10)
Customer #
Key Attributes
PIC 16 Bit 32MHz 51 TQFP-64(10x10) Microcontrollers RoHS
Datasheetpdf iconMICROCHIP PIC24FJ128GB106-I/PT

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerMICROCHIP
PackagingTQFP-64(10x10)
ADC (Bit)10bit
Operating Temperature-40℃~+85℃
Voltage - Supply2V~3.6V
Program Memory TypeFLASH
EEPROM-
Program Storage Size128KB
CPU CorePIC
Core Size16 Bit
CPU Maximum Speed32MHz
Oscillator TypeBuilt-in
Number of I/O51
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging160
Sales UnitPiece

Features

AI Translation
  • On-Chip 2.5V Voltage Regulator
  • Switch between Clock Sources in Real Time
  • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up
  • Run mode: 1 mA/MIPS, 2.0V Typical
  • Sleep mode Current Down to 100 nA Typical
  • Standby Current with 32 kHz Oscillator: 2.5 μA, 2.0V typical
  • USB v2.0 On-The-Go (OTG) Compliant
  • Dual Role Capable – can act as either Host or Peripheral
  • Low-Speed <1.5 Mb/s> and Full-Speed (12 Mb/s) USB Operation in Host mode
  • Full-Speed USB Operation in Device mode
  • High-Precision PLL for USB
  • Internal Voltage Boost Assist for USB Bus Voltage Generation
  • Interface for Off-Chip Charge Pump for USB Bus Voltage Generation
  • Supports up to 32 Endpoints (16 bidirectional): - USB Module can use any RAM location on the device as USB endpoint buffers
  • On-Chip USB Transceiver with On-Chip Voltage Regulator
  • Interface for Off-Chip USB Transceiver
  • Supports Control, Interrupt, Isochronous and Bulk Transfers
  • On-Chip Pull-up and Pull-Down Resistors
  • Modified Harvard Architecture
  • Up to 16 MIPS Operation at 32 MHz
  • 8 MHz Internal Oscillator
  • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier
  • 32-Bit by 16-Bit Hardware Divider
  • 16 x 16-Bit Working Register Array
  • C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes
  • Linear Program Memory Addressing, Up to 12 Mbytes
  • Linear Data Memory Addressing, Up to 64 Kbytes
  • Two Address Generation Units for Separate Read and Write Addressing of Data Memory
In-Stock: 48
48 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 9.9768$ 9.98
10+$ 8.9254$ 89.25
30+$ 8.2858$ 248.57
100+$ 7.7471$ 774.71
Standard Packaging160/Full Tray
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