ISSI IS66WVE4M16EBLL-70BLI

The IS66/67WVE4M16EALL/BLL/CLL and IS66/67WVE4M16TALL/BLL/CLL integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes: Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on an asynchronous memory bus, PSRAM products incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration registers (CR) defines how the PSRAM device performs onchip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. Special attention has been focused on current consumption during self-refresh. This product includes two system-accessible mechanisms to minimize refresh current. Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the CR.

• Asynchronous and page mode interface
• Dual voltage rails for optional performance
  • ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
  • BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
  • CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
• Page mode read access
  • Interpage Read access: 60ns, 70ns
  • Intrapage Read access: 25ns
• Low Power Consumption
  • Asynchronous Operation <30 mA
  • Intrapage Read <23 mA
  • Standby <200 uA (max.) at -40℃~85℃
  • Deep power-down (DPD)
    • ALL/CLL: <3uA (Typ)
    • BLL: <10uA (Typ)
• Low Power Feature
  • Temperature Controlled Refresh
  • Partial Array Refresh
  • Deep power-down (DPD) mode
• Operating temperature Range
  • Industrial: -40℃~85℃
  • Automotive A1: -40℃~85℃
  • Automotive A2: -40℃~105℃
• Packages: 48-ball TFBGA