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ST STM32H723ZEI6
| Manufacturer | |
| MPN | STM32H723ZEI6 |
| LCSC Part # | C730143 |
| Packaging | UFBGA-144 |
| Customer # | |
| Key Attributes | High-performance and DSP with DP-FPU, Arm Cortex-M7 MCU with 512 Kbytes Flash, 564 Kbytes RAM, 550 MHz CPU, L1 cache, external memory interface, subset of peripherals |
| Datasheet |  ST STM32H723ZEI6 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | ST | |
| Packaging | UFBGA-144 | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 12bit;16bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.62V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 512KB | |
| CPU Core | ARM Cortex-M7 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 550MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 114 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2496 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
32-bit Arm Cortex-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
Features
AI Translation
- 32-bit Arm Cortex-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Up to 1 Mbyte of embedded Flash memory with ECC SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes)
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
- 2 x Octo-SPI interface with XiP
- 2 x SD/SDIO/MMC interface
- Bootloader
- Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load
- LCD-TFT controller supporting up to XGA resolution
- 1.62 V to 3.6 V application supply and I/O
- POR, PDR, PVD and BOR
- Dedicated USB power
- Embedded LDO regulator
- Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
- External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE
- Sleep, Stop and Standby modes
- V BAT supply for RTC, 32x32 -bit backup registers
- 2x16 -bit ADC, up to 3.6 MSPS in 16-bit: up to 18 channels and 7.2 MSPS in doubleinterleaved mode
- 1x12 -bit ADC, up to 5 MSPS in 12-bit, up to 12 channels
- 2x comparators
- 2x operational amplifier GBW = 8 MHz
- 2x 12-bit D/A converters
- 8 channels/4 filters
- 4 DMA controllers to offload the CPU
- 1 x MDMA with linked list support
- 2x dual-port DMAs with FIFO
- 1x basic DMA with request router capabilities
- Seventeen 16-bit (including 5x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- 2x watchdogs, 1x SysTick timer
- SWD and JTAG interfaces
- 2-Kbyte embedded trace buffer
- Up to 114 I/O ports with interrupt capability
- Up to 5x I2C FM+ interfaces (SMBus/PMBus)
- Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART
- Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5x SPI (from 5x USART when configured in synchronous mode)
- 2x SAI (serial audio interface)
- 1x FD/TT-CAN and 2xFD-CAN
- 8- to 14-bit camera interface
- 16-bit parallel slave synchronous interface
- SPDIF-IN interface
- HDMI-CEC
- Ethernet MAC interface with DMA controller
- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY
- SWPMI single-wire protocol master I/F
- MDIO slave interface
- CORDIC for trigonometric functions acceleration
- FMAC: Filter mathematical accelerator
- True random number generator
- CRC calculation unit
- RTC with sub-second accuracy and hardware calendar
- ROP, PC-ROP, tamper detection
- 96-bit unique ID
- All packages are ECOPACK2 compliant
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 13.8076 | $ 13.81 |
| 200+ | $ 5.3447 | $ 1068.94 |
| 500+ | $ 5.1558 | $ 2577.90 |
| 1,000+ | $ 5.0637 | $ 5063.70 |
Standard Packaging2496/Full Tray | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | ST | |
| Packaging | UFBGA-144 | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 12bit;16bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.62V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 512KB | |
| CPU Core | ARM Cortex-M7 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 550MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 114 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2496 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
32-bit Arm Cortex-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
Features
AI Translation
- 32-bit Arm Cortex-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Up to 1 Mbyte of embedded Flash memory with ECC SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes)
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
- 2 x Octo-SPI interface with XiP
- 2 x SD/SDIO/MMC interface
- Bootloader
- Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load
- LCD-TFT controller supporting up to XGA resolution
- 1.62 V to 3.6 V application supply and I/O
- POR, PDR, PVD and BOR
- Dedicated USB power
- Embedded LDO regulator
- Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
- External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE
- Sleep, Stop and Standby modes
- V BAT supply for RTC, 32x32 -bit backup registers
- 2x16 -bit ADC, up to 3.6 MSPS in 16-bit: up to 18 channels and 7.2 MSPS in doubleinterleaved mode
- 1x12 -bit ADC, up to 5 MSPS in 12-bit, up to 12 channels
- 2x comparators
- 2x operational amplifier GBW = 8 MHz
- 2x 12-bit D/A converters
- 8 channels/4 filters
- 4 DMA controllers to offload the CPU
- 1 x MDMA with linked list support
- 2x dual-port DMAs with FIFO
- 1x basic DMA with request router capabilities
- Seventeen 16-bit (including 5x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- 2x watchdogs, 1x SysTick timer
- SWD and JTAG interfaces
- 2-Kbyte embedded trace buffer
- Up to 114 I/O ports with interrupt capability
- Up to 5x I2C FM+ interfaces (SMBus/PMBus)
- Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART
- Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5x SPI (from 5x USART when configured in synchronous mode)
- 2x SAI (serial audio interface)
- 1x FD/TT-CAN and 2xFD-CAN
- 8- to 14-bit camera interface
- 16-bit parallel slave synchronous interface
- SPDIF-IN interface
- HDMI-CEC
- Ethernet MAC interface with DMA controller
- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY
- SWPMI single-wire protocol master I/F
- MDIO slave interface
- CORDIC for trigonometric functions acceleration
- FMAC: Filter mathematical accelerator
- True random number generator
- CRC calculation unit
- RTC with sub-second accuracy and hardware calendar
- ROP, PC-ROP, tamper detection
- 96-bit unique ID
- All packages are ECOPACK2 compliant
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |