STC Micro IAP15W4K61S4-30I-LQFP48

The STC15 series is an enhanced 8051-core MCU, operating 7–12× faster than traditional 8051 and 20% faster than STC's earlier 1T series. It features wide voltage range (2.5V–5.5V), low-power design (slow, idle, and power-down modes), and requires no external reset or crystal oscillator, thanks to its built-in high-reliability reset circuit and high-precision R/C clock. It supports power-down wake-up and offers multiple on-chip memory types (Flash, EEPROM, RAM) with high endurance erase/write cycles. The series provides ISP/IAP capability, high-speed ADC, comparator, PWM, timer/counter peripherals, as well as SPI and UART communication interfaces. The instruction set is compatible with standard 8051 and includes hardware multiply/divide instructions. General-purpose I/O pins support multiple configurable modes.

• Large on-chip RAM data memory: 4096 bytes
• High-speed: 1 clock/machine cycle, enhanced 8051 core, 7~12x faster than standard 8051, also 20% faster than STC's early 1T series MCUs (e.g., STC12/11/10 series)
• Wide voltage range: 2.5V~5.5V
• Low-power design: slow mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
• No external reset required; 16 selectable reset threshold voltages during ISP programming; built-in high-reliability reset circuit
• No external crystal required; internal clock configurable from 5MHz~30MHz during ISP programming (equivalent to standard 8051: 60~360MHz); internal high-precision R/C oscillator (±0.3%); temperature drift ±1% (-40℃~+85℃); ±0.6% at room temperature (-20℃~+65℃)
• Power-down wake-up sources: INT0/INT1 (rising/falling edge), INT2/INT3/INT4 (falling edge); pins CCP0/CCP1/RxD/RxD2/RxD3/RxD4/T0/T1/T2/T3/T4; dedicated internal power-down wake-up timer
• On-chip Flash program memory: 16/32/40/48/56/58K/61K/63.5K bytes, endurance >100,000 erase/write cycles
• Large on-chip EEPROM, endurance >100,000 erase/write cycles
• ISP/IAP — in-system/in-application programmable, no programmer/emulator required
• High-speed ADC: 8-channel 10-bit, up to 300,000 samples/sec; 8-channel PWM also usable as 8-channel D/A
• Comparator: usable as 1-channel ADC and for power-down detection; supports comparison between external pin CMP+ and external pin CMP-, or between CMP+ and internal reference voltage; interrupt generation supported; output available on pin CMPO (configurable polarity)
• 6-channel 15-bit dedicated high-precision PWM (with dead-band control) + 2-channel CCP (high-speed pulse output enables 2-channel 11~16-bit PWM) — usable as 8-channel D/A, or 2× 16-bit timers, or 2× external interrupts (rising/falling edge)
• 7 timers/counters total: five 16-bit auto-reload timers/counters (T0/T1/T2/T3/T4; T0 and T1 compatible with standard 8051); all support clock output; pin SysClkO provides divided system clock output (÷1, ÷2, ÷4, or ÷16)
• Programmable clock output (divided from internal system clock or external clock input): T0 on P3.5; T1 on P3.4; T2 on P3.0; T3 on P0.4; T4 on P0.6 — all five timers/counters support 1~65536 division; system clock output on P5.4/SysClkO (STC15 series 8-pin MCUs output main clock on P3.4/MCLKO)
• 4× ultra-high-speed UARTs — four fully independent high-speed async serial ports; time-division multiplexing supports up to 9 virtual serial ports
• SPI high-speed synchronous serial interface
• Hardware WDT
• Advanced instruction set, compatible with standard 8051; hardware multiply/divide instructions
• General-purpose I/O: 62/46/42/38/30/26 pins; default after reset: quasi-bidirectional/weak pull-up (standard 8051 I/O mode); four configurable modes: quasi-bidirectional/weak pull-up, strong push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin can sink/source up to 20mA; total chip current must not exceed 120mA
• No external crystal or external reset required; capable of outputting clock and active-low reset signals
• Unbreakable encryption — Macrocrystal 9th-generation encryption technology
• Ultra-strong interference immunity: high ESD protection, passes 20kV ESD test; passes 4kV EFT test; wide voltage range tolerates power supply noise; wide temperature range -40℃~+85℃
• Significantly reduced EMI: configurable internal clock; 1 clock/machine cycle; supports low-frequency clock operation
• Ultra-low power consumption: power-down mode wake-up current <0.4µA; idle mode typical current <1mA; normal operating current 4mA~6mA; power-down mode wake-up via external interrupt or dedicated internal timer — suitable for battery-powered systems
• In-system emulation and in-system programming; no dedicated programmer or emulator required; supports remote firmware upgrade
• High-speed: 1 clock/machine cycle, enhanced 8051 core, 6~12x faster than standard 8051, also 20% faster than STC's early 1T series MCUs (e.g., STC12/11/10 series)
• Wide voltage range: 2.4V~5.5V
• Low-power design: slow mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
• No external reset required; 16 selectable reset threshold voltages during ISP programming; built-in high-reliability reset circuit
• No external crystal required; internal clock configurable from 5MHz~35MHz during ISP programming (equivalent to 8051: 60~420MHz); internal high-precision R/C oscillator (±0.3%); temperature drift ±1% (-40℃~+85℃); ±0.6% at room temperature (-20℃~+65℃)
• Power-down wake-up sources: INT0/INT1 (rising/falling edge), INT2/INT3/INT4 (falling edge); pins T0/T2; dedicated internal power-down wake-up timer
• On-chip Flash program memory: 1K/2K/3K/4K/5K/7K bytes, endurance >100,000 erase/write cycles
• On-chip RAM data memory: 128 bytes
• On-chip EEPROM, endurance >100,000 erase/write cycles
• ISP/IAP — in-system/in-application programmable, no programmer/emulator required
• Two 16-bit auto-reload timers T0/T2 with clock output capability; pin MCLKO provides divided internal main clock output (÷1, ÷2, or ÷4)
• Programmable clock output (divided from internal system clock or external clock input): T0 on P3.5; T2 on P3.0; internal main clock output on P3.4/MCLKO (STC15 series MCUs with more than 8 pins output main clock on P5.4/MCLKO)
• Hardware WDT
• UART function implementable via [P3.0/INT4, P3.1] combined with a timer
• Advanced instruction set, compatible with standard 8051; hardware multiply/divide instructions
• General-purpose I/O: 8 pins; default after reset: quasi-bidirectional/weak pull-up