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Nexperia 74ALVC164245DGG:11 product image
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Nexperia 74ALVC164245DGG:11RoHS

Manufacturer
Nexperia
MPN
74ALVC164245DGG:11
LCSC Part #
C5531
Packaging
TSSOP-48
Customer #
Key Attributes
16-bit dual supply translating transceiver; 3-state
Datasheetpdf iconNexperia 74ALVC164245DGG:11
In-Stock: 10,660
10,660 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.9864$ 0.9766$ 0.98
10+$ 0.8109$ 0.8028$ 8.03
30+$ 0.7231$ 0.7159$ 21.48
100+$ 0.637$ 0.6307$ 63.07
500+$ 0.507$ 0.5020$ 251.00
1,000+$ 0.4794$ 0.4747$ 474.70
Standard Packaging2000/Full Reel

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Translators, Level Shifters
ManufacturerNexperia
PackagingTSSOP-48
output typeTri-State
Output Signal-
Operating Temperature-40℃~+125℃
Input Signal-
Data Rate-
Number of Elements2
Channel TypeBidirectional
FeaturesPower-off protection;Output enable high-impedance
Voltage - Supply1.5V~5.5V;1.5V~3.6V
Number of Circuits8
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) ≥ VCC(A) (except in suspend mode).

Features

AI Translation
  • Wide supply voltage range:
    • 3 V port (VCC(A)): 1.5 V to 3.6 V
    • 5 V port (VCC(B)): 1.5 V to 5.5 V
  • CMOS low power consumption
  • Overvoltage tolerant inputs to 5.5 V
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Control inputs voltage range from 2.7 V to 5.5 V
  • High-impedance outputs when VCC(A) or VCC(B) = 0 V
  • Complies with JEDEC standards:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

AI Translation
  • Interface between 3 V and 5 V buses
  • Configurable as two 8-bit transceivers or one 16-bit transceiver
  • Suitable for mixed 3 V and 5 V supply environments