WCH CH554E

The CH554 is an enhanced E8051 core MCU compatible with the MCS51 instruction set, with 79% of its instructions being single-byte single-cycle instructions, achieving an average instruction speed 8~15 times faster than standard MCS51. The CH554 supports a maximum system clock frequency of 24MHz, with a built-in 16K program ROM, 256-byte internal iRAM, and 1K-byte on-chip xRAM with DMA support. The CH554 integrates ADC, capacitive touch key detection, 3 timer/capture/PWM units, dual UART, SPI, and other functional modules, with support for both USB-Host and USB-Device modes.

• Core: Enhanced E8051 core, MCS51 instruction set compatible; 79% of instructions are single-byte single-cycle, average instruction speed 8~15x faster than standard MCS51; dedicated XRAM fast data copy instruction; dual DPTR pointers.
• ROM: 16KB reprogrammable non-volatile ROM — fully usable as program storage, or partitioned into 14KB program area and 2KB BootLoader/ISP area.
• DataFlash: 128-byte rewritable non-volatile data memory, supports byte-level data modification.
• RAM: 256-byte internal iRAM for fast data buffering and stack; 1KB on-chip xRAM for large data buffering and DMA access.
• USB: Integrated USB controller and transceiver; supports USB-Host and USB-Device modes; supports USB Type-C host/device detection; supports USB 2.0 full-speed 12Mbps or low-speed 1.5Mbps; max 64-byte packet size; built-in FIFO with DMA support.
• Timer: 3 timers — T0/T1/T2 are standard MCS51 timers.
• Capture: Timer T2 extended to support 2-channel signal capture.
• PWM: 2 PWM outputs — PWM1/PWM2, dual 8-bit PWM outputs.
• UART: 2 async serial ports, both supporting higher baud rates; UART0 is standard MCS51 serial port.
• SPI: SPI controller with built-in FIFO; clock frequency up to half of system clock Fsys; supports simplex multiplexed serial data I/O; supports Master/Slave mode.
• ADC: 4-channel 8-bit ADC with voltage comparison support.
• Touch-Key: 6-channel capacitive sensing; supports up to 15 touch keys; supports independent timer interrupt.
• GPIO: Up to 17 GPIO pins (including XI/XO, RST, and USB signal pins).
• Interrupt: 14 interrupt sources — 6 MCS51-compatible interrupts (INT0, T0, INT1, T1, UART0, T2) plus 8 extended interrupts (SPI0, TKEY, USB, ADC, UART1, PWMX, GPIO, WDOG); GPIO interrupt selectable from 7 pins.
• Watch-Dog: 8-bit presettable watchdog timer WDOG with timer interrupt support.
• Reset: 4 reset sources — built-in power-on reset; software reset and watchdog overflow reset; optional external pin reset input.
• Clock: Built-in 24MHz clock source; external crystal supported via multiplexed GPIO pins.
• Power: Built-in 5V-to-3.3V LDO regulator; supports 5V, 3.3V, or 2.8V supply voltage; supports low-power sleep; wake-up via USB, UART0, UART1, SPI0, and selected GPIO pins.
• On-chip unique ID.