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Nexperia 74AXP8T245BQJ product image
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Nexperia 74AXP8T245BQJRoHS

Manufacturer
Nexperia
MPN
74AXP8T245BQJ
LCSC Part #
C546419
Packaging
DHVQFN-24-EP(3.5x5.5)
Customer #
Key Attributes
8 DHVQFN-24-EP(3.5x5.5) Buffers, Drivers, Receivers, Transceivers RoHS
Datasheetpdf iconNexperia 74AXP8T245BQJ
In-Stock: 21
21 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 1.1595$ 1.16
10+$ 1.1326$ 11.33
30+$ 1.1152$ 33.46
100+$ 1.0978$ 109.78
Standard Packaging3000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerNexperia
PackagingDHVQFN-24-EP(3.5x5.5)
Data Rate-
Voltage - Supply900mV~5.5V;900mV~5.5V
Operating Temperature-40℃~+125℃
Output Signal-
Output TypeTri-State
Input Signal-
Channel TypeBidirectional
Number of Elements-
FeaturesPower-off protection;Output enable high-impedance
Number of Channels8
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

The 74AXP8T245 is an 8-bit dual supply translating transceiver with 3-state outputs that enable bidirectional level translation. It features two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.9 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power supply sequencing is required and output glitches during power supply transitions are prevented using patented circuitry. As a result glitches will not appear on the outputs for supply transitions during power-up/down between 20 mV/μs and 5.5 V/s. Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

Features

AI Translation
  • Wide supply voltage range: VCC(A): 0.9 V to 5.5 V; VCC(B): 0.9 V to 5.5 V
  • Low input capacitance; C1 = 1.5 pF (typical)
  • Low output capacitance; C0 = 3.8 pF (typical)
  • Low dynamic power consumption; CPD = 10 pF (typical)
  • Low static power consumption; ICC = 2 μA (25 ℃ maximum)
  • High noise immunity
  • Complies with JEDEC standard: JESD8-12 (1.1 V to 1.3 V; inputs), JESD8-11 (1.4 V to 1.6 V), JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD12-6 (4.5 V to 5.5 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2 kV; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1 kV
  • Latch-up performance exceeds 100 mA per JESD78D Class II
  • Inputs accept voltages up to 5.5 V
  • Low noise overshoot and undershoot < 10% of VCC0
  • IOFF circuitry provides partial power-down mode operation
  • Specified from -40 ℃ to +125 ℃