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Nexperia 74HC273D-Q100J product image
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Nexperia 74HC273D-Q100JRoHS

Manufacturer
Nexperia
MPN
74HC273D-Q100J
LCSC Part #
C546790
Packaging
SO-20-300mil
Customer #
Key Attributes
2V~6V 8 1 15ns@4.5V,50pF SO-20-300mil Flip Flops RoHS
Datasheetpdf iconNexperia 74HC273D-Q100J
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QtyUnit Price(Reference Only)Total Amount
1+$ 0.2408$ 0.24
10+$ 0.1939$ 1.94
30+$ 0.1738$ 5.21
100+$ 0.1487$ 14.87
500+$ 0.1375$ 68.75
1,000+$ 0.1308$ 130.80
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerNexperia
PackagingSO-20-300mil
Operating Temperature-40℃~+125℃
Voltage - Supply2V~6V
Number of Bits per Element8
Series74HC Series
Output Type-
Number of Elements1
Current - Output High(IOH)4mA
Current - Output Low(IOL)4mA
Quiescent Current8uA
Setup Time4ns
Hold Time3ns
Propagation Delay15ns@4.5V,50pF
Trigger TypeRising Edge
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

AI Translation
  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40°C to +85°C and from -40°C to +125°C
  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V)
  • Input levels:
    • For 74HC273-Q100: CMOS level
    • For 74HCT273-Q100: TTL level
  • Common clock and master reset
  • Eight positive edge-triggered D-type flip-flops
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • Multiple package options
  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints